Raiden Mark III - greater RISC, greater reward
I selected ARM processors for Raiden Mark II for a number of reasons, but one of the most important ones was that I was under the impression that there was an open-source implementation of the ARM CPU and by selecting this as the foundation of Raiden, I could maximize flexibility (as well as control) in future iterations. As it turns out, that was not completely correct. There are indeed open-source ARM processors (which can be implemented in silicon or synthesized via FPGA, etc.) however the “modern” ARM CPU (including the ones I’m using in Raiden Mark II) are proprietary, and there is no real hope that these designs will become open in the future. This doesn’t change my immediate plans because a proprietary ARM processor still achieves the primary goals I have for Raiden Mark II, but it does impact plans I have for the next iteration of Raiden, Mark III. The good news is that as I was discovering that ARM isn’t going to provide everything I need, there is another RISC architecture that does, and it will be available as a component similar to the ARM SOC I’m using in Raiden II. This new architecture is RISC-V, and it is a completely open design. RISC-V processors are currently available however they are aimed at the embedded market (think Arduino). That said, there is already Linux kernel support for RISC-V, and a four-core system-on-a-chip capable of running Linux is expected to ship in the first quarter of 2018. In addition to production chips realized in silicon, there are RISC-V cores available which can be synthesized via FPGA, and this is of particular interest to me because I have planned to make FPGA fabric a key component of Raiden Mark III since the beginning. It’s not clear to me yet whether a hybrid SOC+FPGA or pure FPGA RISC-V implementation is the right choice for Raiden Mark III, but what is clear is that going forward, the CPU architecture of choice for Raiden will be RISC-V.